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clang ships ppc_wrappers/{x,e,p,t,s,n}mmintrin.h that implement the
SSE..SSE4.2 intrinsics on top of VSX (POWER8 and later), which is the
ISA level the SSE4.2 kernels need. Treat powerpc64 hosts like the
AArch64 path: define the x86 ISA macros by hand in clang.cmake, mark the
platform as 64-bit, report SSE4.2 features at runtime, and opt into the
wrapper headers from platform.h so that every translation unit including
embree headers gets them. The few intrinsics the wrappers lack
(_mm_popcnt_u32/u64, _mm_dp_ps, _mm_insert_ps, _mm_stream_load_si128)
and the MXCSR control family (no POWER equivalent; FTZ/DAZ become
no-ops) get small definitions in intrinsics.h.
Tested with clang 19 on FreeBSD powerpc64le and powerpc64 (big-endian):
the ANARI SDK helide device renders all 13 of its test scenes
pixel-identical to an x86-64 build.
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clang ships ppc_wrappers/{x,e,p,t,s,n}mmintrin.h that implement the
SSE..SSE4.2 intrinsics on top of VSX (POWER8 and later), which is the
ISA level the SSE4.2 kernels need. Treat powerpc64 hosts like the
AArch64 path: define the x86 ISA macros by hand in clang.cmake, mark the
platform as 64-bit, report SSE4.2 features at runtime, and opt into the
wrapper headers from platform.h so that every translation unit including
embree headers gets them. The few intrinsics the wrappers lack
(_mm_popcnt_u32/u64, _mm_dp_ps, _mm_insert_ps, _mm_stream_load_si128)
and the MXCSR control family (no POWER equivalent; FTZ/DAZ become
no-ops) get small definitions in intrinsics.h.
Tested with clang 19 on FreeBSD powerpc64le and powerpc64 (big-endian):
the ANARI SDK helide device renders all 13 of its test scenes
pixel-identical to an x86-64 build.